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<p><strong>ITAR Notice:</strong> This role involves access to ITAR-controlled information. Applicants must be U.S. persons (U.S. citizens, U.S. permanent residents, asylees, or refugees) per 22 CFR 120.62.</p>
<h3 class="p1">What will you do:</h3>
<p class="p1">Land somewhere across the DensityAI hardware org — RTL design, design verificaCon (SOC, AI Core, formal, or general DV), physical design, DFT / manufacturing test, performance modeling and verificaCon, advanced packaging, or post-silicon bring-up.</p>
<p class="p2"><span class="s2">The specialized roles are posted separately; this one is for engineers who span more than one of them,</span> <span class="s2">or who don't fit one lane cleanly. We'll do the sub-team match during interviews.</span></p>
<p class="p3"><span class="s3">Use</span> <span class="s3">and</span> <span class="s3">develop</span> <span class="s3">AI</span> <span class="s3">assisted</span> <span class="s3">tool</span> <span class="s3">flows</span> <span class="s3">to</span> <span class="s3">accelerate</span> <span class="s3">whichever</span> <span class="s3">discipline</span> <span class="s3">you</span> <span class="s3">land</span> <span class="s3">in.</span></p>
<h3 class="p4"><span class="s5"><strong>What</strong></span><span class="s6"><strong> </strong></span><span class="s5"><strong>we're</strong></span><span class="s6"><strong> </strong></span><span class="s5"><strong>looking</strong></span><span class="s6"><strong> </strong></span><span class="s5"><strong>for:</strong></span></h3>
<ul>
<li><span class="s5">You bring exceptional SystemVerilog and Verilog skills at production grade, and you're comfortable reading complex testbenches and the RTL they exercise</span></li>
<li><span class="s5">You have 5+ years of production silicon experience, including at least one production tape-out that you contributed to meaningfully — with responsibility that extended into post-silicon debug</span></li>
<li><span class="s5">You understand the end-to-end ASIC flow, from RTL through synthesis, place & route, and signoff</span></li>
<li><span class="s5">You have strong computer-architecture fluency across pipelines, caches, memory hierarchies, and NoC topologies</span></li>
<li><span class="s5">You're comfortable with ambiguity — the specific sub-team match happens during the interview process</span></li>
<li><span class="s5">(Optional) It's a plus if you bring experience with UVM and constrained-random verification, formal methods (SVA, JasperGold, VC Formal), industry-standard EDA tools (VCS, Verdi, Innovus, Fusion Compiler, PrimeTime, Tempus, Tessent), advanced process nodes (7nm or better), DFT methodology, multi-die packaging (CoWoS, EMIB, 2.5D/3D, HBM), signal/power integrity, RISC-V, performance modeling, or scripting (Python, Tcl)</span></li>
</ul><div class="content-pay-transparency"><div class="pay-input"><div class="description"><p>Full compensation packages are based on candidate experience and relevant certifications. </p></div><div class="title">California pay range</div><div class="pay-range"><span>$70,000</span><span class="divider">—</span><span>$70,000 USD</span></div></div></div>
